Semiconductor component manufacturers typically make a plurality of semiconductor components from a single semiconductor wafer. The number of integrated circuits that can be manufactured from the single semiconductor wafer ranges from one up to tens of thousands. Because integrated circuits are comprised of transistors or semiconductor devices, one technique for lowering their cost of manufacture is to shrink the transistor sizes, which in turn shrinks the integrated circuit sizes. Manufacturing costs are lowered because more integrated circuits can be manufactured from each semiconductor wafer. Another advantage of shrinking transistor sizes is that their operating speeds increase.
A drawback with shrinking transistors is that the surface of the semiconductor wafer becomes non-planar which may limit the resolution of the photolithography processes used in integrated circuit manufacture. Non-planar surfaces that arise during manufacture can create imperfections such as voids in layers subsequently formed over the non-planar surfaces. Voids degrade integrated circuit performance. FIG. 1 illustrates a portion of a prior art Electrically Erasable and Programmable Read Only Memory (“EEPROM”) 10 during an intermediate stage of manufacture. EEPROM 10 comprises a semiconductor substrate 12 having a major surface 14 and Shallow Trench Isolation (“STI”) structures 16A, 16B, and 16C. STI structure 16A separates active regions 17A and 17B from each other, STI structure 16B separates active regions 17B and 17C from each other, and isolation structure 16C separates active regions 17C and 17D from each other. A layer of dielectric material 18 is formed on major surface 14. Floating gates 20, 22, 24, and 26 are disposed on portions of dielectric layer 18 and are spaced apart from each other. Preferably, floating gates 20–26 are formed over respective active regions 17A–17D. Because of the small device sizes and the short distance between isolation structures, surface non-planarity may cause floating gates 20–26 to be misaligned. This misalignment decreases the reliability of EEPROM 10.
Floating gates 22 and 26 are shown as being misaligned in FIG. 1 such that floating gate 22 has an edge or side near an edge of isolation structure 16B and floating gate 26 has an edge or side near an edge of isolation structure 16C. An Oxide-Nitride-Oxide (“ONO”) dielectric structure 30 is formed on floating gates 20–26. A layer of polysilicon 32 having a surface 34 is disposed on dielectric structure 30. Although not shown for the sake of clarity, it should be understood that polysilicon layer 32 is patterned to serve as a word line of EEPROM 10. The misalignment of floating gate 22 causes a portion of polysilicon layer 32 to be sufficiently close to one edge of floating gate 22 and isolation structure 16B to stress it during operation. Likewise, the misalignment of floating gate 26 causes another portion of polysilicon layer 32 to be sufficiently close to one edge of floating gate 26 and isolation structure 16C to stress it during operation. The increased stress decreases the reliability of the semiconductor component and may result in failure of EEPROM 10.
Accordingly, what is needed is a semiconductor component and method for its manufacture that improves surface planarity and mitigates misalignment of structures such as floating gates.